Building a Dynamically Reconfigurable System Through a High Development Flow
D. Fuente de San Venancio; J. Barba; X. Peña; J.C. López; P. Peñil; P. Sánchez
Cenference: International Forum on Design Languages
Location: Barcelona (España)
Date: 14/09/2015 - 16/09/2015
Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, such as the reduction of the total area required in a FPGA by means of functioning overlapping, or the modification of the design after its deployment, where a complete configuration is not needed. However, the design of partially reconfigurable systems is still a complex task. This work focuses on facilitating the design process and proposes a new development framework for dynamically configurable systems from high level UML/MARTE models which, starting from dynamically reconfigurable systems high level UML/MARTE models. Simulation and VHDL code are generated from those models, according to the specification requirements of the reconfigurable hardware captured in the specifications.