Sphere Detector For 802.16e Broadband Wireless Systems Implementation On FPGAs Using High-Level Synthesis Tools
J.J. Noguera; S. Neuendorffer; S.V. Haastregt; J. Barba; K. Vissers; C. Dick
Cenference: SDR Wireless Innovation Conference and Product Exposition
Location: Washington DC (Estados Unidos)
Date: 30/11/2010 - 03/12/2010
Pages: 547-552
In this paper we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using High-level Synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and automatically generate a Register Transfer Level (RTL) descripcion for FPGA implementation using traditional FPGA implementation tools. We have used AutoESLs AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225MHz. The obtained results show that these modern high-level synthesis tools produce Quality of Results (QoR) competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details.