Development flow for FPGA-based scalable reconfgurable systems
Development flow for FPGA-based scalable reconfgurable systems
J. Caba; J.D. Dondo; F. Rincón; J. Barba; J.C. López
Cenference: Euromicro Conference on Digital System Design
Location: Santander (Spain)
Date: 04/09/2013 - 06/09/2013
Pages: 666-669
ISBN: 978-0-7695-5074-9
Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, for instance we can change a part of the initial functionality after its deployment, where a complete configuration is not needed, and the total area required is reduced. However, the design of partially reconfigurable systems has been a complex task yet. This work try to facilitate the design process and proposes a new development flow, which reduces mistakes during first stages of the design and makes the building of partial reconfiguration projects easier. In addition, we provide a dedicated hardware component, which manages bitstreams and dynamic areas. This component speed up the reconfiguration time, accomplishing a speed about 180MB/s.